AI Infrastructure
Architecture Study. This is a hypothetical system study. The numbers, topology, and traffic patterns are illustrative and do not describe any specific employer or production deployment. The goal is to reason from first principles about a class of problem that recurs across large sparse-model serving systems.
We studied a hypothetical inference platform serving an AI-powered search answer generation experience — the kind that returns a synthesized, cited answer rather than a list of links — at a scale of billions of requests per day with a sub-second p99 latency target.
The model is a 235B-parameter Mixture-of-Experts (MoE) decoder served across a fleet of NVIDIA H100 GPUs. Our initial capacity model assumed GPU compute would be the dominant bottleneck, so the scaling plan was simple: add GPUs, get throughput.
It did not work. Doubling GPUs from 128 to 256 returned roughly 1.2× more throughput, not 2×. Profiling showed the GPUs were frequently idle, waiting — not on compute, but on the expert-routing traffic that MoE generates on every decode step. The bottleneck had quietly moved from the silicon into the network fabric.
This article walks the investigation end to end: the business framing, the baseline assumptions, the benchmarks, the profiling, the root cause, and the production-grade mitigations — topology design, communication-library tuning, fleet placement, and monitoring — with an emphasis on the NVIDIA GPU and networking stack (NVLink, NVSwitch, InfiniBand, NCCL, NVSHMEM, GPUDirect RDMA, and DCGM).
Before any architecture, the business shape of the problem dictates the constraints.
An answer-generation search surface has an unusual cost profile:
A dense model large enough to give good answers is economically painful here: every token activates every parameter, so cost scales with full model size on every request. MoE is attractive precisely because it decouples capacity from per-token compute — a 235B-parameter model might activate only ~20B parameters per token by routing each token to a small number of specialized experts. On paper, you get the quality of a large model at the compute cost of a small one.
The catch — and the subject of this study — is that the routing which makes MoE cheap in FLOPs makes it expensive in communication.
Figure 1. The request lifecycle. Compute stages look local; the expert-parallel group hides a network underneath.
A request flows through a frontend router (auth, routing, SLO enforcement), into a continuous batcher that interleaves prefill and decode work to keep GPUs busy, and into the MoE decoder. The decoder runs attention locally, then a top-k gating network selects which experts each token should visit.
Because the 235B parameters do not fit on one GPU, experts are sharded across the fleet using expert parallelism (EP): each GPU owns a subset of experts. When a token is routed to an expert living on a different GPU — which is the common case — its activations must be sent there and the result sent back. That movement is the hidden network we will spend the rest of the article on.
Writing down what we expected before measuring is what makes the surprise legible.
We assumed:
Every one of these turned out to be wrong at scale, in ways that compounded.
We built a realistic but hypothetical test bed:
| Component | Configuration |
|---|---|
| GPUs | 64 → 512 NVIDIA H100 (80 GB SXM) |
| Node | 8× H100, NVSwitch all-to-all, ~900 GB/s NVLink per GPU |
| Inter-node fabric | NVIDIA Quantum-2 InfiniBand, NDR 400 Gb/s (ConnectX-7) |
| Parallelism | Expert Parallel = 16, Tensor Parallel = 8 |
| Comms | NCCL with GPUDirect RDMA |
| Workload | decode-heavy, short prompts, streaming answers |
The workload matters: answer generation is decode-heavy. Decode emits one token at a time, so each step moves small tensors very frequently. Hold that thought — it is the crux of the root cause.
We scaled the fleet with the model and traffic mix held constant and measured relative throughput:
| GPUs | Expected (linear) | Measured |
|---|---|---|
| 64 | 1.0× | 1.0× |
| 128 | 2.0× | 1.7× |
| 256 | 4.0× | 2.1× |
| 512 | 8.0× | 2.25× |
Figure 2. Throughput decouples from GPU count. The widening gap is the cost of communication, not a shortage of compute.
The curve flattens hard. By 512 GPUs we were paying for 8× the hardware to get a little over 2× the work. GPU utilization counters, meanwhile, looked fine on average — which is exactly how this class of bug hides.
We started where the assumptions pointed. Using Nsight Systems to capture a timeline and DCGM for fleet-wide counters:
# Per-rank timeline with NVTX ranges and NCCL/cuDNN traces
nsys profile -t cuda,nvtx,nccl -o decode_step \
--capture-range=cudaProfilerApi python serve_decode.py
The kernels were healthy: attention and FFN GEMMs hit expected SM occupancy, HBM bandwidth was nowhere near saturated, and there were no obvious stalls inside the compute kernels. Average SM utilization looked acceptable — but the timeline told a different story: long, recurring gaps between kernels, aligned across ranks. The GPUs were synchronized in their idleness.
Next we instrumented the gating network and logged per-expert token counts. Routing was not uniform. With learned top-2 gating, a handful of experts attracted disproportionate traffic:
expert_load (tokens/step, normalized):
E0:1.0 E1:0.9 ... E17:6.1 ... E63:0.4
Expert 17 was receiving roughly 6× the average load. Token routing in trained MoE models is rarely balanced in practice; popularity is data-dependent and drifts over time. A hot expert means a hot destination on the network.
The aligned idle gaps plus a hot destination pointed straight at the fabric. We read InfiniBand port and switch counters and NCCL transport stats:
NCCL_DEBUG=INFO NCCL_DEBUG_SUBSYS=NET python serve_decode.py
perfquery -x # IB port counters: xmit/rcv data, wait, congestion
The fabric showed the signature of congestion: rising switch-buffer occupancy, PFC pause frames (RoCE) / congestion-control throttling (InfiniBand), and ECN marks concentrated on the links feeding the hot experts. The story had begun.
The decode loop most engineers picture is compute: attention → FFN → next token. The loop that actually governs throughput is communication:
Figure 3. Every decode step contains two network collectives — dispatch and combine — repeated for every output token.
Each decode step performs two all-to-all collectives:
In NVIDIA's stack these are typically realized as a grouped sequence of
ncclSend/ncclRecv calls (an all-to-all-v pattern) so that each rank can send
different amounts to different peers — because, as we saw, the distribution is uneven.
Intra-node hops ride NVLink/NVSwitch; inter-node hops ride InfiniBand with
GPUDirect RDMA, so the NIC reads and writes GPU memory directly without bouncing
through the CPU.
The critical property: in decode, each of these transfers is small (one token's hidden state per expert) but extremely frequent (twice per token). That makes the all-to-all latency- and message-rate-bound, not bandwidth-bound. You can have terabytes per second of fabric bandwidth sitting idle while throughput collapses, because the limiter is how many small messages per second the fabric and NICs can push — and how long the slowest one takes.
Four effects compound:
Hot experts. Learned routing concentrates traffic on a few experts. Their host GPUs become network destinations far above the average.
Incast. In a single step, many source GPUs send to the same hot expert at the same time. Their flows converge on one switch egress port, overflowing its buffer.
Figure 4. Incast: synchronized convergence onto a popular expert saturates a single port, triggering pause/ECN and stalling its senders.
Collective amplification. One routing decision per token fans out into many small transfers across the fabric. Sparse routing turns a compute choice into a communication storm.
Tail latency dominance. A collective is a barrier: the step cannot finish until every transfer completes. One congested port — the slowest expert's link — gates the entire step. This is why average utilization looked healthy while throughput suffered: the tail, not the mean, sets the pace.
Zoom out and the geometry gets worse. A flat all-to-all over N GPUs creates on the order of N² small inter-node flows. As N grows:
The takeaway: beyond a node, throughput is a function of the network topology and the traffic's locality, not of the GPU count.
There is no single fix. We treated this as a portfolio of changes, each a tradeoff.
Topology-aware expert placement. Place frequently co-activated experts within the same NVLink island so their traffic never touches the fabric. Pro: removes inter-node hops for the hottest paths. Con: placement must track drifting routing distributions; stale placement decays.
Expert replication for hot experts. Replicate the few popular experts across nodes and load-balance across replicas to break the incast. Pro: directly attacks the hotspot. Con: costs memory and adds a consistency/ routing-decision surface.
Hierarchical all-to-all. Aggregate token transfers within a node over NVLink, do a single fat inter-node exchange over InfiniBand, then scatter within the destination node — instead of every GPU talking to every remote GPU directly.
Figure 5. Hierarchical all-to-all collapses many tiny inter-node messages into few large ones, trading message rate for bandwidth — the right trade for a fabric that is message-rate-bound.
Pro: converts a message-rate problem into a bandwidth problem the fabric is good at; libraries such as NVSHMEM-based dispatch and modern expert-parallel comm kernels exploit exactly this. Con: added kernel complexity and an extra on-node staging step.
Topology-aware / adaptive routing in the fabric. Enable InfiniBand adaptive routing and tune congestion control (DCQCN/ECN/PFC for RoCE) so converging flows spread across paths rather than piling onto one. Pro: mitigates incast without code changes. Con: tuning is workload-specific and can interact badly with bursty traffic if misconfigured.
Rail-optimized network design. Home each GPU's NIC to its own rail (leaf), so an all-to-all maps onto parallel, independent rails instead of one shared bottleneck. NCCL's PXN (PCI × NVLink) path keeps traffic rail-local.
Figure 6. Rail-optimized topology. GPU index i always egresses on rail i, so synchronized all-to-all traffic is spread across rails by construction.
Pro: structural — the topology itself prevents a class of hotspot. Con: it is a data-center build decision, hard to retrofit.
Communication-library tuning. NCCL exposes the knobs that decide whether small collectives are fast:
# Prefer low-latency protocols for small decode messages
export NCCL_PROTO=LL128
# Keep transfers on GPUDirect RDMA; never bounce via host
export NCCL_NET_GDR_LEVEL=PHB
# Pin to the rail-local HCA and raise channel count for parallelism
export NCCL_IB_HCA=mlx5
export NCCL_MIN_NCHANNELS=8
# Allow PXN rail-local routing
export NCCL_PXN_DISABLE=0
Pro: large gains for zero hardware cost. Con: values are topology- and shape-specific; the right setting at 128 GPUs may be wrong at 512.
Note on SHARP. NVIDIA's in-network reduction (SHARP) accelerates reductions such as the all-reduce in tensor-parallel layers, but it does not accelerate the all-to-all that MoE dispatch/combine relies on. It is worth enabling for the parts of the model that reduce — just don't expect it to fix the MoE hotspot.
In large-scale sparse models, the dominant bottleneck is increasingly communication, not computation. The more we sparsify and distribute a model to save FLOPs, the more we spend on moving activations — and that spending lands on the network.
Said differently: MoE trades compute for communication. That trade is usually a win, but it relocates the bottleneck from a place we instrument well (the GPU) to a place we instrument poorly (the fabric, the tail, the incast). The engineering discipline that matters at scale is communication-aware system design.
The same physics will shape what comes next:
A benchmark fix is not a production fix. Three practices kept the gains in production.
Continuous profiling. Capture periodic per-rank nsys timelines and NVTX-annotated
collective spans on a sample of the fleet, so a regression in all-to-all time is caught
as a metric, not a customer complaint.
Fleet and topology management. The scheduler is topology-aware: jobs are placed in rail-aligned placement groups, hot-expert replicas are spread across failure domains, and nodes showing fabric degradation are drained rather than left to gate collectives for everyone sharing their step.
Production monitoring. The dashboards that mattered were not GPU utilization — they were network signals:
dcgmi dmon) correlated with the above.The guiding principle: measure the network and the tail, because the mean will lie to you.
This is part of an ongoing architecture-study series. Corrections and counterpoints are welcome — the goal is to reason in public about how large AI systems actually behave under load.